Integrated circuits having transistors with high holding voltage and methods of producing the same

ABSTRACT

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a source in electrical communication with the substrate. A drain is also in electrical communication with the substrate. A gate overlies the substrate between the source and the drain, wherein a channel is defined within the substrate directly underlying the gate, and where a Schottky portion of the substrate is positioned between the channel and the source.

TECHNICAL FIELD

The technical field generally relates to integrated circuits havingtransistors with high holding voltages and methods of producing thesame, and more particularly relates to integrated circuits withtransistors having Schottky barriers that increase the holding voltage,and methods of producing the same.

BACKGROUND

Integrated circuits often include a plurality of pins that are used tomake electrical connections to components beyond the integrated circuit,such as a power pin for supplying power, a ground pin for groundingpurposes, and a signal pin. Exemplary signal pins include an inputsignal pin for supplying an external signal to the integrated circuitand an output signal pin for outputting a signal from the integratedcircuit. Typically, a gate grounded transistor is electrically connectedbetween different pins for electrostatic discharge protection, so anintegrated circuit with three pins would have at least three gategrounded transistors electrically connected between the pins. These gategrounded transistors discharge excess voltage that may arise due to anelectrostatic discharge or other types of electrical noise.

The gate grounded transistor has a holding voltage that is an inherentfeature of the transistor, where the “holding voltage” is the minimumvoltage that must be applied for an electronic device to remain in the“on” state. Many typical gate grounded transistors have a holdingvoltage of about 6 volts, but other designs may have other holdingvoltages. The holding voltage should be at or above the operatingvoltage for the integrated circuit to prevent undesirable trips of thegate grounded transistor. For example, if the operating voltage of anintegrated circuit was 6 volts, minor voltage variations over time (i.e.“noise”) could frequently trip the gate grounded transistor with aholding voltage of 6 volts because there is essentially no safety marginbetween the holding voltage and the operating voltage. Furthermore, thedesigned operating voltage may be limited by the holding voltage of gategrounded transistors used for electrostatic discharge protection.

Accordingly, it is desirable to provide integrated circuits withtransistors that have higher holding voltages than traditionaltransistors, where these transistors may be used for electrostaticdischarge protection, and methods of producing the same. In addition, itis desirable to develop transistors for electrostatic dischargeprotection that do not increase the manufacturing processes needed toproduce an integrated circuit. Furthermore, other desirable features andcharacteristics of the present embodiment will become apparent from thesubsequent detailed description and the appended claims, taken inconjunction with the accompanying drawings and this background of theinvention.

BRIEF SUMMARY

Integrated circuits and methods of producing the same are provided. Inan exemplary embodiment, an integrated circuit includes a substrate anda source in electrical communication with the substrate. A drain is alsoin electrical communication with the substrate. A gate overlies thesubstrate between the source and the drain, wherein a channel is definedwithin the substrate directly underlying the gate, and where a Schottkyportion of the substrate is positioned between the channel and thesource.

An integrated circuit is provided in another embodiment. The integratedcircuit includes a substrate and a source in electrical communicationwith the substrate. A drain is also in electrical communication with thesubstrate, where a source to drain length is measured from the source tothe drain. A gate overlies the substrate, and two spacers are adjacentto opposite sides of the gate. A channel is defined within the substratedirectly underlying the gate and the two spacers, where the channel hasa channel length that is less than the source to drain length.

A method of producing an integrated circuit is provided in yet anotherembodiment. The method includes forming a gate overlying a substrate,and forming a source and a drain within the substrate on opposite sidesof the gate where a Schottky portion of the substrate is positionedbetween the gate and the source. A Schottky barrier is formed at theSchottky portion of the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The present embodiments will hereinafter be described in conjunctionwith the following drawing figures, wherein like numerals denote likeelements, and wherein:

FIGS. 1-11 illustrate, in cross sectional views, an integrated circuitand methods for fabricating the same in accordance with exemplaryembodiments, where a portion of FIG. 11 includes an electrical schematicto illustrate an embodiment of electrical connections; and

FIG. 12 is an electrical schematic of an embodiment of a portion of anintegrated circuit.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and isnot intended to limit the various embodiments or the application anduses thereof. Furthermore, there is no intention to be bound by anytheory presented in the preceding background or the following detaileddescription. Embodiments of the present disclosure are generallydirected to integrated circuits and methods for fabricating the same.The various tasks and process steps described herein may be incorporatedinto a more comprehensive procedure or process having additional stepsor functionality not described in detail herein. In particular, varioussteps in the manufacture of integrated circuits are well-known and so,in the interest of brevity, many conventional steps will only bementioned briefly herein or will be omitted entirely without providingthe well-known process details.

Reference is made to an exemplary embodiment illustrated in FIG. 1. Anintegrated circuit 10 has a substrate 12 that includes semiconductormaterial. As used herein, the term “semiconductor material” will be usedto encompass semiconductor materials conventionally used in thesemiconductor industry from which to make electrical devices.Semiconductor materials include monocrystalline silicon materials, suchas the relatively pure or lightly impurity-doped monocrystalline siliconmaterials typically used in the semiconductor industry, as well aspolycrystalline silicon materials, and silicon admixed with otherelements such as germanium, carbon, and the like. In addition,“semiconductor material” encompasses other materials such as relativelypure and impurity-doped germanium, gallium arsenide, zinc oxide, glass,and the like. As referred to herein, a material that includes a recitedelement/compound includes the recited element/compound in an amount ofat least 10 weight percent or more based on the total weight of thematerial unless otherwise indicated. In many embodiments, the substrate12 primarily includes a monocrystalline semiconductor material. Thesubstrate 12 may be a bulk silicon wafer (as illustrated) or may be athin layer of silicon on an insulating layer (commonly known assilicon-on-insulator or SOI, not illustrated) that, in turn, issupported by a carrier wafer. In an exemplary embodiment, the substrate12 has a planar surface, as illustrated.

A shallow trench isolation structure 14 may be positioned within thesubstrate 12, where the shallow trench isolation structure 14 is anelectrical insulator. As used herein, an “electrically insulatingmaterial” or an “electrical insulator” is a material with a resistivityof about 1×10⁴ ohm meters or more, an “electrically conductive material”is a material with a resistivity of about 1×10⁻⁴ ohm meters or less, andan “electrically semiconductive material” is a material with aresistivity of from more than about 1×10⁻⁴ ohm meters to less than about1×10⁴ ohm meters. In an exemplary embodiment the shallow trenchisolation structure 14 includes silicon dioxide, but other electricallyinsulating materials may be present in alternate embodiments. A surfacedielectric layer 16 may overlie the substrate 12 in some embodiments,where the surface dielectric layer 16 includes silicon dioxide in anexemplary embodiment but may include other materials in alternateembodiments. As used herein, the term “overlying” means “over” such thatan intervening layer may lie between the surface dielectric layer 16 andthe substrate 12, or “on” such that the surface dielectric layer 16physically contacts the substrate 12. Moreover, the term “directlyoverlying” means a vertical line passing through the upper componentalso passes through the lower component, such that at least a portion ofthe upper component is directly over at least a portion of the lowercomponent. It is understood that the integrated circuit 10 may be movedsuch that the relative “up” and “down” positions change, so reference toa “vertical” line means a line that is about perpendicular to thesurface of the substrate 12.

Referring to the exemplary embodiment in FIG. 2, a base well 18 isformed in the substrate 12. The base well 18 may be formed by implantingconductivity determining impurities. The conductivity determiningimpurities may be implanted into the base well 18 at a base wellconcentration, such as a base well concentration of from about 1×10¹⁴ toabout 1×10¹⁶ per cubic centimeter, but other concentrations are alsopossible. The conductivity determining impurities may be implanted asions under the influence of an electrical field. In an exemplaryembodiment, the conductivity imparting impurities are “P” typeconductivity determining impurities, where “P” type conductivitydetermining impurities primarily include boron, aluminum, gallium, andindium, but other materials could also be used in alternate embodiments.“N” type conductivity determining impurities may be implanted in analternate embodiment, where “N” type conductivity determining impuritiesprimarily include phosphorous, arsenic, and/or antimony, but othermaterials could also be used.

A gate layer 20 and a gate mask layer 22 may be formed overlying thesubstrate 12, as illustrated in an embodiment in FIG. 3. The gate layer20 may include polysilicon, which can be formed by low pressure chemicalvapor deposition using silane, but other deposition techniques ormaterials may be used in alternate embodiments. The gate mask layer 22may be formed overlying the gate layer 20, where the gate mask layer 22includes silicon nitride in an exemplary embodiment. Silicon nitride canbe formed by low pressure chemical vapor deposition using ammonia anddichlorosilane, but other materials or other deposition techniques maybe used in alternate embodiments. A gate photoresist layer 24 may beformed and patterned overlying the gate mask layer 22. The gatephotoresist layer 24 (and other photoresist layers described below) maybe deposited by spin coating, and patterned by exposure to light orother electromagnetic radiation through a mask with transparent sectionsand opaque sections. The light causes a chemical change in thephotoresist such that either the exposed portion or the non-exposedportion can be selectively removed. The desired locations may be removedwith an organic solvent, and the gate photoresist layer 24 remainsoverlying the other areas of the gate mask layer 22 and the gate layer20. The gate photoresist layer 24 (and other photoresist layersdescribed below) may optionally include a top and/or bottomanti-reflective coating (not illustrated). Many anti-reflective coatingsare available, including inorganic and organic compounds, such astitanium nitride or organosiloxanes. Titanium nitride may be depositedby chemical vapor deposition using tetramethylamidotitanium and nitrogentrifluoride, and organosiloxanes may be deposited by spin coating.Anti-reflective coatings may improve the accuracy and criticaldimensions during photoresist patterning.

Reference is made to an embodiment illustrated in FIG. 4, withcontinuing reference to FIG. 3. The gate mask layer 22, the gate layer20, and the surface dielectric layer 16 that are not covered by thepatterned gate photoresist layer 24 may be removed to form a gate 30 anda gate dielectric 32. In an embodiment where the gate mask layer 22primarily includes silicon nitride, the exposed portions can be removedwith a wet etch using hot phosphoric acid where the remaining portionsare used to shield underlying materials for subsequent etchings. Theexposed portions of the gate layer 20 may be removed with a reactive ionetch using hydrogen bromide for a gate layer 20 primarily includingpolysilicon, and the surface dielectric layer 16 may be removed with awet etch using dilute hydrofluoric acid for embodiments where thesurface dielectric layer 16 primarily includes silicon dioxide. However,many etchant techniques and materials are available, so other techniquesand/or materials may be used in alternate embodiments. In an embodiment,the remaining gate photoresist layer 24 is removed with an oxygencontaining plasma, and the remaining gate mask layer 22 is removed witha wet etch using hot phosphoric acid, but other etchants can be used inalternate embodiments.

Referring to an exemplary embodiment in FIG. 5, an extension photoresistlayer 26 is formed and patterned overlying a portion of the substrate12. The substrate 12 directly adjacent to one side of the gate 30 isexposed and the substrate 12 directly adjacent to the opposite side ofthe gate 30 is covered by the extension photoresist layer 26.Conductivity determining impurities may be implanted into the exposedsubstrate 12 to form a drain extension 28, where a portion of the gate30 may directly overlie a portion of the drain extension 28. Ionimplantation may be used to form the drain extension 28, and theimplantation process may result in some ions travelling into thesubstrate 12 and under adjacent structures, such as the gate 30 in anexemplary embodiment.

A spacer layer 34 may be formed overlying the gate 30 and the substrate12 in an exemplary embodiment illustrated in FIG. 6. The spacer layer 34may include silicon nitride in an exemplary embodiment, but otherelectrically insulating materials may be used in alternate embodiments.The horizontal portions of the spacer layer 34 may be removed with ananisotropic etch to leave two spacers 36 adjacent to opposite sidesurfaces of the gate 30 and the gate dielectric 32, as illustrated inFIG. 7 with continuing reference to FIG. 6. A dry plasma etch withhydrogen and nitrogen trifluoride may be used, but other etch techniquesor materials are also possible. The anisotropic etch is stopped when thehorizontal portions of the spacer layer 34 (the portions that areparallel with the surface of the substrate 12) are removed, but beforethe vertical portions adjacent to the gate 30 are removed.

Referring to an exemplary embodiment illustrated in FIG. 8, a Schottkyphotoresist layer 40 is formed and patterned to overlay a portion of thesubstrate 12 adjacent to the gate 30 and the spacer 36. The Schottkyphotoresist layer 40 may be the same photoresist layer used for othermanufacturing processes, such as isolation of “P” type transistorsduring source/drain dopant implantation. As such, the Schottkyphotoresist layer 40 may not require an additional manufacturing processover standard complementary metal oxide semiconductor (CMOS)manufacturing techniques. The Schottky photoresist layer 40 is used toform a Schottky area, as described below, hence the use of the term“Schottky.” A Schottky barrier is a potential energy barrier formed atthe junction between a metal and a semiconductor. Schottky barriers haverectifying characteristics, and may be used as diodes in some cases.

A source 42 and a drain 44 may be formed in the substrate 12 byimplantation of conductivity determining impurities, as illustrated inFIG. 9 with continuing reference to FIG. 8. The source 42 and drain 44may include “N” type conductivity determining impurities in an exemplaryembodiment, but the source 42 and drain 44 may also include “P” typeconductivity determining impurities in an alternate embodiment. Thedrain extension 28 is in electrical communication with the drain 44, andmay physically contact the drain 44, but the drain 44 does not directlyunderlie the gate 30. In an alternate embodiment (not illustrated), thesource 42 and/or drain 44 may be formed in electrical communication withthe substrate 12 without being formed within the substrate 12, but thesource 42 and drain 44 are in electrical communication with thesubstrate 12. The term “electrical communication,” as used herein, meanselectrical current is capable of flowing from one component to another,where the electrical current may or may not flow through an electricallyconductive intervening component. The term “direct electrical contact,”as used herein, means direct physical contact between components thatare electrically conductive or semiconductors, but not electricalinsulators. The conductivity imparting impurities are implanted into thedrain 44 directly adjacent to the spacer 36 and the gate, but a Schottkyportion 48 of the substrate 12 separates the source 42 from the spacer36 and the gate 30. The Schottky portion 48 of the substrate 12 is aportion of the substrate 12 that is between the source 42 and the drain44 but does not directly underlie the gate 30 or the spacer 36.

A channel 46 is defined within the substrate 12 between the source 42and the drain 44, where the channel 46 directly underlies the gate 30and the spacers 36 (in embodiments where spacers 36 are present). An ESDtransistor 62 includes the gate 30, the source 42, the drain 44, and thechannel 46. The Schottky portion 48 of the substrate 12 is positionedbetween the source 42 and the gate 30, as described above, so the gate30 does not directly overlie the Schottky portion 48 of the substrate12. The spacers 36 also do not directly overlie the Schottky portion 48of the substrate 12, in embodiments where spacers 36 are present. TheSchottky portion 48 and the substrate 12 include conductivity impartingimpurities at a concentration that is less than that of the source 42and/or drain 44. The Schottky portion 48 and the substrate 12 may bedefined within the base well 18, so the Schottky portion 48 and thesubstrate 12 may include conductivity imparting impurities at about thesame concentration as in the base well 18. The source 42, the drain 44,the channel 46, and the base well 18 are all in electricalcommunication.

The integrated circuit 10 has a source to drain length 50 measured fromthe source 42 to the drain 44, and the channel 46 has a channel length52 extending from a side of the spacer 36 directly adjacent to the drain44 to the opposite side of the other spacer 36 that is adjacent to theSchottky portion 48 of the substrate 12. As such, the channel length 52includes the length of the gate 30 and the two adjacent spacers 36, orthe channel length 52 includes the length of only the gate 30 inembodiments where no spacers 36 are present. The channel length 52 isless than the source to drain length 50. The Schottky portion 48 of thesubstrate 12 has a Schottky length 54 extending from the source 42 tothe edge of the closest spacer 36, or to the edge of the gate 30 inembodiments without a spacer 36. In an exemplary embodiment, theSchottky length 54 is from about 0.1 to about 0.5 micrometers, but otherSchottky lengths 54 are also possible in alternate embodiments. Thesource to drain length 50 is about the sum of the channel length 52 andthe Schottky length 54. The Schottky portion 48 of the substrate 12separates the source 42 from the gate 30 and the spacer 36.

Referring to an exemplary embodiment illustrated in FIG. 10, a groundphotoresist layer 60 is formed and patterned overlying the source 42,the drain 44, the Schottky portion 48, and the gate 30. The groundphotoresist layer 60 is patterned to expose a portion of the base well18 on an opposite side of the shallow trench isolation structure 14 fromthe source 42. Referring to FIG. 11 with continuing reference to FIG.10, a ground region 64 is formed within the substrate 12 and the basewell 18 by implanting conductivity determining impurities. Theconductivity determining impurities within the ground region 64 may bethe opposite type as in the source 42 and drain 44, so in an exemplaryembodiment the ground region 64 may include “P” type conductivitydetermining impurities when the source 42 and drain 44 include “N” typeconductivity determining impurities. The ground region 64 is inelectrical communication with the ESD transistor 62 through the basewell 18 in an exemplary embodiment.

A plurality of contacts may be formed, where the contacts areillustrated in schematic form in FIG. 11. The contacts may include aground contact 70, a source contact 72, a Schottky contact 74, a gatecontact 76, and a drain contact 78, where the contacts are in electricalcommunication with the ground region 64, the source 42, the Schottkyportion 48, the gate 30, and the drain 44, respectively. Some of thecontacts listed above may not be present in all embodiments, and theremay be a plurality of some of the contacts listed above in someembodiments.

The source contact 72 and the Schottky contact 74 are in electricalcommunication, and it may even be possible to utilize a single contactin electrical communication with both the source 42 and the Schottkyportion 48 of the substrate 12 in some embodiments. However, referenceto the Schottky contact 74 and the source contact 72 together indicatesat least two different contacts are present for the source 42 and theSchottky portion 48 of the substrate 12. The Schottky portion 48 of thesubstrate 12 is a semiconductor, and the Schottky contact 74 (and theother contacts described herein) is a conductive material such as ametal, so a Schottky barrier is formed in embodiments where the Schottkycontact 74 directly contacts the Schottky portion 48 of the substrate12. A silicide (not illustrated) may be formed on the surface of theSchottky portion 48 in some embodiments, but the silicide has a highconductivity and a Schottky barrier is still formed in embodiments witha silicide on the surface of the Schottky portion 48. The silicide, ifpresent, may directly contact the Schottky contact 74 such that theSchottky portion 48 is in electrical communication with the Schottkycontact 74. This Schottky barrier may drain excess current when the ESDtransistor 62 is tripped, and this may increase the holding voltage ofthe ESD transistor 62 over similar transistors that do not include aSchottky portion 48 of the substrate 12.

Reference is made to an exemplary embodiment illustrated in FIG. 12,with continuing reference to FIG. 11, where FIG. 12 is a schematic typefigure. The integrated circuit 10 includes a plurality of pins, such asa first pin 80, a second pin 82, and a third pin 84, and the integratedcircuit 10 may include additional pins in some embodiments. In anexemplary embodiment, the first pin 80, the second pin 82, and the thirdpin 84 are selected from a power pin, a ground pin, and a signal pin,but other embodiments are also possible. An ESD transistor 62 iselectrically connected between each pin, so an ESD transistor 62 iselectrically connected between the first and second pins 80, 82, anotherESD transistor 62 is electrically connected between the second and thirdpins 82, 84, and yet another ESD transistor 62 is electrically connectedbetween the third and first pins 84, 80. For an ESD transistor 62electrically connected between the first and second pins 80, 82, thesource 42 of the ESD transistor 62 is connected to one of the pins, suchas the first pin 80, and the drain 44 of the ESD transistor 62 isconnected to the other pin, such as the second pin 82. Similarconnections for the other ESD transistors 62 are also utilized. In someembodiments, different types of pins are connected to an individual ESDtransistor 62, but two pins of the same type may be connected to anindividual ESD transistor 62 in other embodiments. The higher holdingvoltage of the ESD transistors 62 may allow for fewer unintended tripsof the ESD transistor 62, or it may allow for a higher operating voltagefor the integrated circuit 10.

While at least one exemplary embodiment has been presented in theforegoing detailed description, it should be appreciated that a vastnumber of variations exist. It should also be appreciated that theexemplary embodiments are only examples, and are not intended to limitthe scope, applicability, or configuration of the application in anyway. Rather, the foregoing detailed description will provide thoseskilled in the art with a convenient road map for implementing one ormore embodiments, it being understood that various changes may be madein the function and arrangement of elements described in an exemplaryembodiment without departing from the scope, as set forth in theappended claims.

1. An integrated circuit comprising: a substrate; a source in electricalcommunication with the substrate; a drain in electrical communicationwith the substrate; a gate overlying the substrate between the sourceand the drain, wherein a channel is defined within the substratedirectly underlying the gate, and wherein a Schottky portion of thesubstrate is positioned between the channel and the source; a base welldefined within the substrate, wherein the channel is defined within thebase well; and a ground contact electrically connected to the base well.2. The integrated circuit of claim 1 wherein the Schottky portion of thesubstrate is from about 0.1 to about 0.5 microns.
 3. The integratedcircuit of claim 15 further comprising: a base well defined within thesubstrate, wherein the channel is defined within the base well.
 4. Theintegrated circuit of claim 1 wherein the Schottky portion of thesubstrate is defined within the base well.
 5. The integrated circuit ofclaim 20 further comprising forming a source contact in electricalcommunication with the source, wherein the source contact and theSchottky contact are in electrical communication.
 6. The integratedcircuit of claim 1 further comprising: a source contact in electricalcommunication with the source; and a Schottky contact in electricalcommunication with the Schottky portion, wherein the source contact andthe Schottky contact are in electrical communication.
 7. The integratedcircuit of claim 1 further comprising: two spacers adjacent to the gate,wherein the gate and the two spacers directly overlie the channel. 8.The integrated circuit of claim 1 wherein: the substrate comprises aplanar surface, and the gate overlies the planar surface.
 9. Theintegrated circuit of claim 1 further comprising: a Schottky contact inelectrical communication with the Schottky portion.
 10. The integratedcircuit of claim 1 wherein the source comprises N type conductivitydetermining impurities and the drain comprises N type conductivitydetermining impurities.
 11. The integrated circuit of claim 3 furthercomprising a ground region in electrical communication with the basewell.
 12. The integrated circuit of claim 1 further comprising: a firstpin electrically connected to the source; a second pin electricallyconnected to the drain.
 13. The integrated circuit of claim 12 whereinthe first pin is selected from a power pin, a ground pin, and a signalpin.
 14. The integrated circuit of claim 13 wherein the second pin isselected from the power pin, the ground pin, and the signal pin, andwherein the first pin and the second pin are different from each other.15. An integrated circuit comprising: a substrate; a source inelectrical communication with the substrate; a drain in electricalcommunication with the substrate; a gate overlying the substrate betweenthe source and the drain, wherein a channel is defined within thesubstrate directly underlying the gate, and wherein a Schottky portionof the substrate is positioned between the channel and the source; andwherein the source comprises N type conductivity determining impuritiesand the drain comprises N type conductivity determining impurities. 16.The integrated circuit of claim 20 further comprising: forming a basewell in the substrate, wherein the channel is defined within the basewell.
 17. The integrated circuit of claim 15 wherein the Schottkyportion has a Schottky length of from about 0.1 to about 0.5 microns.18. The integrated circuit of claim 16 further comprising forming aground region within the substrate, wherein the ground region is inelectrical communication with the base well.
 19. The integrated circuitof claim 15 further comprising: a first pin; and a second pin, whereinthe first pin and the second pin are electrically connected by an ESDtransistor, wherein the ESD transistor comprises the source, the drain,and the gate.
 20. A method of producing an integrated circuitcomprising: forming a gate overlying a substrate, wherein a channel isdefined within the substrate directly underlying the gate; forming asource and a drain within the substrate on opposite sides of the gate,wherein a Schottky portion of the substrate is positioned between thegate and the source; and forming a Schottky contact in electricalcommunication with the Schottky portion.